Fidelity under readout, drive, and circuit noise (09/09/26)

TL;DR Without a Josephson parametric amplifier, the 4 K $\mathrm{InP}$ HEMT LNA (channel high-electron-mobility transistor low-noise amp) dominates readout noise; qubit-loop IQ histograms overturn Y-factor ranking and show assignment fidelity ${\mathcal{F}}_a$ peaking at 60% channel In, often at roughly an order of magnitude below typical dc bias power.

• Method: A qubit-in-the-loop benchmark ranks cryogenic LNAs by the two-dimensional IQ histogram of single-shot dispersive readout (in-phase/quadrature clouds that set SNR and state assignment), not by standalone Y-factor noise temperature $T_N$ (hot/cold load thermometry).
• Devices: Three state-of-the-art cryogenic $\mathrm{InP}$ HEMT LNAs with 53%, 60%, and 70% channel indium, plus a commercial reference, are compared in the same superconducting-qubit readout chain.
• Ranking mismatch: The 60% and 70% devices show similar $T_N$, both better than 53%, and the 70% device has the highest gain, yet readout SNR and assignment fidelity ${\mathcal{F}}_a$ (correct $|0⟩$/$|1⟩$ label rate from the IQ clouds) instead peak at 60%.
• Power map: ${\mathcal{F}}_a$ does not simply saturate with HEMT dc power and, for several devices, falls above a device-dependent bias well below typical operating points.
• Hardware takeaway: The best overall device (60%) needs about $1\mathrm{mW}$ for ${\mathcal{F}}_a>85\%$; across all four LNAs, ${\mathcal{F}}_a>80\%$ appears at as little as about $0.3\mathrm{mW}$, guiding amp selection and bias under multi-qubit 4 K heat budgets.

TL;DR Strongly driven parametric two-qubit gates are accurately described as coherent rotations between instantaneous eigenstates—not idle ones—with exchange and effective $ZZ$ set by time-derivative couplings from the non-Abelian Berry connection (the geometric connection that couples moving eigenstates under flux change). The framework matches exact numerics across DTC, CSDTC, and STC tunable-coupler architectures, where idle-frame models fail at the large amplitudes needed for fast gates.

• Main result: In the instantaneous eigenbasis $\{|\mathbf{m};\Theta (t)⟩\}$, an optimized parametric iSWAP—an AC-flux-activated $|01⟩\leftrightarrow |10⟩$ swap—stays a clean two-level oscillation, whereas the idle eigenbasis shows a messy trajectory outside that manifold.
• Mechanism: Transitions come from time-derivative couplings ${\Gamma }_{\mathbf{m},\mathbf{l}}=A_{\mathbf{m},\mathbf{l}}(\Theta )\dot{\Theta }$, so the non-Abelian Berry connection $A$ supplies a compact expression for the exchange rate and the driven $ZZ$ phase.
• Hardware scope: Quantitative agreement holds for double-transmon (DTC), capacitively shunted double-transmon (CSDTC), and single-transmon (STC) couplers, including exchange $\Omega$ and accumulated ${\varphi }_{ZZ}$ versus drive amplitude.
• Design implication: Exact exchange ${\Omega }_{\mathrm{ex}}=\pi /(2T)$ exceeds the idle-frame estimate at large amplitude, so gates can run faster than naive idle-point theory predicts once the instantaneous-frame rate is used.
• Nonadiabatic ZZ: Averaged nonadiabatic $ZZ$, ${\bar{\zeta }}_{\mathrm{nonad}}$, is dominated by instantaneous-frame couplings of $|11;\Theta ⟩$ to $|20;\Theta ⟩$ and $|02;\Theta ⟩$, and changes sign near drive frequencies set by the qubit anharmonicities.

TL;DR A deep Q-network agent (DQN: a neural net that scores discrete drive choices from measured Pauli expectations) learns ansatz-free, $1\mathrm{ns}$-step bang-bang pulses for ctrl-VQE—the pulse-level VQE that shapes microwave drives ${\Omega }_q(t)$ instead of compiling gates—on a simulated two-transmon ${\mathrm{H}}_2$ problem. The learned policy beats random search on fidelity and energy error at hardware-compatible timing, and favors mostly idle, sparse drives—useful for cQED calibration when the continuous pulse landscape outruns GRAPE/CRAB-style model-based search.

• Main result: On a fixed-frequency, always-on-coupled two-transmon simulator of ${\mathrm{H}}_2$ at $0.75\mathring{\mathrm{A}}$ (STO-3G), the DQN reaches peak state fidelity $0.9969$ by $\sim 42\mathrm{ns}$ within a $100\mathrm{ns}$ window, while random search stays near $0.991$–$0.992$ and peaks later ($\sim 66\mathrm{ns}$).
• Energy accuracy: Absolute gaps to full configuration interaction (FCI: the exact STO-3G ground energy) fall to $11.52$, $4.82$, and $2.42\mathrm{mHa}$ at $10$, $40$, and $100\mathrm{ns}$ for DQN versus $11.62$, $8.72$, and $6.12\mathrm{mHa}$ for random search; only DQN enters the $5\mathrm{mHa}$ chemical-accuracy band by $40\mathrm{ns}$.
• Hardware loop: Each $1\mathrm{ns}$ step, the agent observes Pauli expectation values and picks one of nine discrete amplitudes $({\Delta }_1,{\Delta }_2)\in \{-1,0,+1{\}}^2$ (full drive, idle, or opposite), matching typical AWG timing and a bang-bang restriction that turns pulse design into a discrete RL search.
• Learned pulses: At $100\mathrm{ns}$, the best DQN sequence idles on $(0,0)$ for $\sim 70\%$ of steps and almost never co-drives both qubits, resembling sparse bang-bang schedules that optimal-control theory often favors for fast state transfer.
• Scope: Training is model-free given a reward from energy drop relative to FCI, but the reported runs are classical Trotter simulations without decoherence or control noise; the authors flag finer or continuous amplitudes and hardware noise as next limits.

TL;DR On superconducting hardware, a distribute–collapse error-detection scheme (encode a control into a GHZ ancilla, then reduce it with local checks and postselection) restores usable long-range entanglement for constant-depth dynamic circuits—mid-circuit measurement plus classical feedforward—without extra ancillas. A 100-qubit-chain Bell pair reaches $F=0.59\pm 0.02$ above the $F>0.5$ entanglement threshold that the baseline dynamic circuit misses ($0.39\pm 0.01$).

• Main result: Error-detected distribute and collapse${}^{(n)}$ (constant-depth GHZ spread of a logical control, then parity reduction with check gadgets $V_n$) trade readout- and fusion-induced infidelity for postselection, with no added ancillas and only constant gate depth.
• Hardware win: On a superconducting processor, an error-detected long-range Bell pair across a 100-qubit chain achieves $F=0.59\pm 0.02$, while the unprotected dynamic-circuit baseline stays at $0.39\pm 0.01$ and fails entanglement certification at $F>0.5$.
• State prep: Constant-depth W-state preparation (equal superposition of single excitations) up to 20 qubits, by consuming GHZ resources up to 40 qubits, gains absolute fidelity $\Delta F\approx 0.2$ at the largest sizes once error detection is on.
• cQED implication: Mid-circuit readout and feedforward latency—often worse than two-qubit gates on superconducting chips—are the bottleneck the scheme targets; implicit checks (redundant $X^{\otimes n}$ extraction that also flags collapse readout errors) typically beat explicit $Z_j{Z}_{j+1}$ stabilizer checks when measurement is noisier than CNOTs.
• Bonus primitive: An error-detected Hadamard test (estimate $\mathrm{Re}⟨\psi |U|\psi ⟩$ via an ancilla interferometer) for an $N$-qubit $U$ of depth $k$ runs in dynamic-circuit depth $O(k)$ with one mid-circuit measurement/feedforward round, versus worst-case unitary depth $O(Nk)$.

TL;DR An even-distance Generalized Superfast Encoding (GSE)—a fermion-to-qubit map whose stabilizers detect and correct errors—yields constant-weight (4 or 6) generators for any even $d$, and simulated circuit-level memory for $[[48,8,6]]$ and $[[64,8,8]]$ shows a threshold near $4\times 10^{-3}$. This is the first fermion-mapping memory result with threshold-like scaling under circuit noise, not mere error detection.

• Main result: Circuit-level depolarizing memory simulations of the even-distance GSE instances $[[48,8,6]]$ and $[[64,8,8]]$ exhibit a threshold $\approx 4\times 10^{-3}$, the first fault-tolerant memory characterization of a fermion-to-qubit encoding with threshold-like scaling.
• Code construction: Each of $N$ fermionic modes sits in a $d$-qubit ring block for even distance $d$; the resulting stabilizers keep weight 4 or 6 independent of $d$.
• Syndrome schedule: The full stabilizer set partitions into four qubit-wise commuting groups, so syndrome extraction remains compact as distance grows.
• Decoder stack: AlphaSyndrome (a scheduler that packs bare-ancilla stabilizer checks into few layers) plus Relay-BP (belief-propagation decoding that relays soft messages across check rounds) underpin the simulated memory experiments.