Planar GKP, LDPC surgery, and cryogenic stacks (09/24/26)

TL;DR A heavy fluxonium—whose bit-flip lifetime $451\pm 70\mu \mathrm{s}$ beats prior bosonic-control qubits—drives an on-chip Archimedean spiral resonator to prepare and stabilize finite-energy Gottesman–Kitaev–Preskill (GKP) codewords, grid states that encode a qubit in oscillator phase space. Measurement-free quantum error correction (QEC) with rapid fluxonium reset extends the logical lifetime by $1.59\pm 0.05$, giving the first standalone bosonic QEC in a fully planar superconducting architecture.

• Architecture: Pairing a weakly coupled heavy fluxonium with a planar Archimedean spiral resonator replaces centimeter-scale 3D cavities and fixed-frequency transmons with a chip-scale mode volume and a much longer control-qubit bit-flip lifetime.
• Main result: Finite-energy GKP states are prepared and stabilized by measurement-free QEC that uses rapid fluxonium reset, extending the logical lifetime by a factor of $1.59\pm 0.05$.
• Control advance: The experiment is the first demonstration of resonator control with a weakly coupled fluxonium in the weak-dispersive regime relevant to planar cQED.
• Hardware significance: Standalone bosonic QEC no longer requires 3D cavities, opening a planar integration path for hardware-efficient fault tolerance.

TL;DR A whole-system cryogenic-wiring model (Cryowala) systematically optimizes coaxial attenuator and cable stacks for millikelvin microwave processors and beats common “best-practice” layouts on mixing-chamber heat, drive/flux noise, and qubit capacity. The optima are context-dependent—challenging the blanket use of 0 dB attenuators (inner-conductor thermalizers with nominally zero attenuation)—and motivate an equal-balance cascade rule analogous to low-noise amplifier chains.

• Main result: Holistic Cryowala sweeps of coaxial drive and flux stacks identify layouts that outperform Krinner-style heuristics on device temperature, noise burden, and cooling-limited qubit capacity on a BlueFors LD-400-class fridge.
• Drive lines: With total attenuation fixed at $60\mathrm{dB}$, a $10$–$20$–$30\mathrm{dB}$ split on the $4\mathrm{K}$, cold-plate (CP), and mixing-chamber (MXC) stages sits in the noise plateau while minimizing cooling consumption.
• Flux lines: Attenuation below the $4\mathrm{K}$ plate is of limited use; a $6$–$14\mathrm{dB}$ split on the $50\mathrm{K}$ and $4\mathrm{K}$ stages matches best-practice noise while staying farther inside the $4\mathrm{K}$ cooling budget.
• 0 dB attenuators: Ideal zero-loss units help thermalize the coax center conductor, but even $A_{\mathrm{real}}=0.1\mathrm{dB}$ residual loss can dump untenable active heat onto the MXC under flux bias.
• Design principle: An attenuator-cascade analysis yields equal-balance heuristics—set stage attenuation so transmitted warmer-stage noise roughly equals added Johnson–Nyquist noise—plus a web tool for context-specific redesign.

TL;DR A frequency-domain inversion and time-domain fitting pipeline builds a compact hybrid IIR–FIR predistortion filter—an infinite/finite impulse-response pair that undoes long-lived flux-line memory from the actual pulse history—so an FPGA can correct synthesized waveforms at $1.2GSa/s$ in real time. On two-qubit cross-entropy benchmarking, that real-time path reaches a median controlled-Z Pauli fidelity near the software-reference $99.57\%$, while hardware cost grows only roughly logarithmically when the compensation window stretches from microseconds to hundreds of microseconds.

• Main result: Real-time hybrid IIR–FIR flux predistortion on an FPGA matches offline software compensation, with median CZ Pauli fidelity close to the $99.57\%$ software reference under two-qubit cross-entropy benchmarking.
• Method: Frequency-domain inversion reconstructs the compensation impulse response; time-domain fitting then compresses it into a compact hybrid IIR–FIR filter that accounts for the pulse history needed by dynamic circuits.
• Throughput: Look-ahead parallelization of the IIR stage plus a sliding-window FIR stage sustains $1.2GSa/s$ waveform synthesis on the FPGA.
• Scaling: Extending the compensation timescale from microseconds to hundred-microsecond windows raises LUT and DSP use by only about $14\%$ and $4\%$, respectively, with relative arithmetic error below $10^{-4}$.
• Hardware takeaway: The logarithmic resource growth with compensation horizon makes long-memory flux correction practical for high-fidelity, history-dependent flux control in dynamic cQED circuits.

TL;DR For any quantum LDPC CSS code $[[n,k,d]]$ (sparse-check Calderbank–Shor–Steane), the authors build a sparse high-rate surgery gadget—an auxiliary system that measures many logical operators in parallel—from linear PCPPs (probabilistically checkable proofs of proximity: randomised verifiers that check a linear circuit’s input via oracle access to the input plus a claimed proof). On any subcode of size $\mu \le n$ holding $t\le k$ logicals, the gadget has size ${\mu }^{1+o(1)}$, near the $\Omega (\mu )$ lower bound, and keeps phenomenological fault distance at least $d$ over $d$ rounds.

• Main result: From linear PCPPs, any $[[n,k,d]]$ quantum LDPC CSS code and any size-$\mu$ subcode with $t$ logicals yields a sparse surgery gadget of size $\mu (\log \mu {)}^{O(\log \log \mu )}={\mu }^{1+o(1)}$ that measures all $t$ logicals in parallel.
• Optimality: Space overhead is asymptotically optimal up to subpolynomial factors, matching the $\Omega (\mu )$ lower bound on auxiliary size for that measurement task.
• Mechanism: Surgery gadgets with relative cosystolic expansion (a local expansion property that keeps sparse checks and fault distance) are constructed by lifting linear PCPPs for the measurement circuit.
• Runtime: The gadget is produced in time polynomial in $\mu$.
• Fault tolerance: Logical measurement with these gadgets preserves phenomenological fault distance at least $d$ when run for $d$ rounds.

TL;DR The authors build length-$n$ quantum LDPC codes—codes whose stabilizers have constant weight—with polynomial distance $d\ge n^{(1-ϵ)/r}$ that implement the non-Clifford multi-controlled phase $C^{r-1}Z$ (phase $-1$ when $r$ qubits are all $|1⟩$) transversally on $k\ge n^{1-ϵ}$ disjoint logical tuples, for every constant $r\ge 3$ and arbitrarily small $ϵ>0$. This is the first constant-weight-stabilizer family with $dk\gg n$, so the magic-state overhead exponent $\gamma =\log (n/k)/\log (d)$ can be driven arbitrarily close to zero.

• Main result: Length-$n$ quantum LDPC codes of distance $d\ge n^{(1-ϵ)/r}$ support transversal $C^{r-1}Z$ on $k\ge n^{1-ϵ}$ disjoint logical tuples, for every fixed $r\ge 3$ and any $ϵ>0$.
• Overhead breakthrough: These codes are the first with constant-weight stabilizers to achieve $dk\gg n$, yielding arbitrarily small magic-state overhead exponent $\gamma =\log (n/k)/\log (d)>0$; prior comparable constructions needed at least polylogarithmic stabilizer weight.
• Linear-rate tradeoff: A companion regime gives $k=\Omega (n)$ logical $C^{r-1}Z$ gates, at the cost of stabilizer weight and physical circuit depth $n^{ϵ}$.
• Mechanism: A cup-product map (the cohomology product that turns classical codeword multiplications into quantum cochain operations) sends classical codes with a multiplication property to quantum codes with transversal $C^{r-1}Z$; the classical inputs are new Tanner codes from punctured tensor products of algebraic codes.
• Addressability: The same transversal gates can target chosen logical qubits rather than acting only as a global block operation.