Certifying Hamiltonians while automating planar layouts
Today splits between quantum information science—how far spectral certificates and many-body control can be pushed—and superconducting qubits tooling that finally emits fab-ready planar geometry. Overlapping Pauli products assemble efficiently checkable lower bounds that track typical random signed -local Pauli ground energies to additive error, yet non-commutative Sum-of-Squares (ncSoS; Sum-of-Squares plus Pauli commutation) still leaves a constant gap on a modified no-low-energy-trivial-states family; in parallel, exchange-only control—gates driven only by voltage-tuned two-spin exchange—uses the full total-spin-zero () singlet manifold of up to 48 electron spins as workspace, with out-of-time-order correlators (OTOCs; forward–backward scrambling probes) showing rich dynamics at an effective error per exchange. On the hardware side, an open-source Munich Quantum Toolkit superconducting physical design flow turns planar circuit quantum electrodynamics (cQED) qubits, couplers, and control lines under real fabrication rules into manufacturing-ready floorplans in seconds to minutes.
Physical Design Automation for Planar Superconducting Quantum Chips
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TL;DR An open-source flow, mqt-scpd (Munich Quantum Toolkit superconducting physical design), turns planar cQED chip layout—qubits, couplers, and control lines under real fabrication design rules—into a fully automatic geometric pipeline that emits manufacturing-ready floorplans in seconds to minutes. That closes the gap between hand layout (days to weeks) and prior automation that dropped physical constraints and never reached fab-ready GDS.
- Problem: Planar superconducting quantum chip (SCQC) layout is still mostly manual; prior automation tools simplify the geometry or relax design-rule constraints and therefore do not deliver fabrication-ready results.
- Abstraction: The authors map device physics—pad clearances, routing channels, and port placement on qubit/coupler cells—into a rigorous geometric formulation so CAD methods can enforce the same rules hardware engineers already check by hand.
- Flow: A three-stage pipeline runs geometry-aware global partitioning (cavity-tree splits around routing bottlenecks), ILP-based port assignment (integer linear programming that chooses which pad each net lands on), then hierarchical routing with conflict resolution.
- Result: Interdisciplinary checks by design-automation and superconducting-hardware experts confirm complete, design-rule-compliant layouts at the push of a button, up to about faster than prior automated baselines on hard instances.
- Release: Methods ship as open-source mqt-scpd inside the Munich Quantum Toolkit—the first end-to-end planar SCQC physical-design flow that keeps the underlying physical constraints explicit.
Spectral Certificates and Non-commutative Sum-of-Squares Lower Bounds for Hamiltonians
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TL;DR A quantum Kikuchi matrix—a spectral certificate assembled from overlapping Pauli products, in the spirit of classical -XOR CSP refutation—yields efficiently checkable lower bounds that, for typical random signed -local Pauli Hamiltonians, track the true ground energy to additive error . The same method fails in the worst case: non-commutative Sum-of-Squares (ncSoS), the Sum-of-Squares hierarchy augmented by Pauli commutation relations, leaves a constant gap even at levels on a modified NLTS (no low-energy trivial states) family that is also NP-hard to approximate and requires circuit depth for all low-energy states.
- Main result: For any constant , an efficiently computable length- spectral certificate is always a valid lower bound on the ground energy of a random -qubit signed -local Pauli Hamiltonian, and with high probability is -accurate once the Hamiltonian has enough terms.
- Method: The certificate comes from a quantum Kikuchi matrix that lifts classical -XOR CSP refutation to -local Pauli Hamiltonians and bounds the ground energy via the matrix's spectral norm.
- Limitation: By construction, the same spectral technique can fail to produce tight certificates on worst-case signed -local Pauli instances.
- Hardness stack: A modification of prior quantum-code NLTS Hamiltonians simultaneously yields -depth lower bounds for all low-energy states, constant-gap NP-hardness of approximating the ground energy, and a constant-gap ncSoS integrality gap through levels.
- Conceptual frame: ncSoS is the standard Sum-of-Squares hierarchy augmented by the commutation relations among Pauli operators, which is what makes the worst-case lower bounds nontrivial.
Benchmarking exchange-only control of a 48-spin singlet manifold
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TL;DR HRL and Microsoft benchmark exchange-only control—gates driven only by voltage-tuned two-spin exchange—across up to 48 electron spins by treating the full total-spin-zero () singlet manifold (Hilbert-space dimension ) as the computational workspace rather than discarding most states as leakage. Out-of-time-order correlators (OTOCs; probes of operator scrambling under forward–backward evolution) show rich scrambling, while generalized cross-entropy and mirror randomized benchmarking yield an effective system-level error of per exchange, up to an order of magnitude below comparable platform-level figures at the time of writing.
- Main idea: Instead of encoding logical qubits in three-spin decoherence-free subsystems and treating the rest of the spin space as leakage, the experiment benchmarks the entire exchange-only array inside the total-spin-zero singlet manifold.
- Scale: Arrays of up to 48 electron spins access an Hilbert space with dimension exceeding , far larger than the subspace of conventional three-spin encodings for spins.
- Scrambling: OTOC measurements expose rich operator-spreading dynamics and reach regimes argued to be relevant to quantum computational advantage.
- Error metric: Generalized cross-entropy benchmarking (XEB; comparing measured bitstring probabilities to ideal circuit predictions) and mirror randomized benchmarking (MRB; random circuits followed by their inverses) give an aggregate error of per two-spin exchange, folding in the full control sequence and all noise sources.
- Comparison: That per-exchange system error is reported as up to about lower than contemporaneous comparable benchmarks on other hardware platforms.